In memory devices, such as dynamic memory devices with read and write access (DRAM), the communication of the memory to the external world is performed with the help of receivers and off-chip drivers (off chip drivers=OCD). The receivers receive the data during the write process, while the off-chip drivers (OCDs) provide the read data to the outside world. With the current strongly increasing data rates, the performance of the off-chip driver (OCD) is increasingly important. Thus, the length of a valid read date in a memory device according to the DDR II (double data rate II) standard, which is driven with a clock frequency of 533 MHz, is less than 940 ps (picoseconds). This corresponds to half a clock period. In this context, this is also referred to as the length of the so-called data eye.
The data eye can be corrupted by several undesirable mechanisms. Here, the mutual interference of simultaneously output read data has to be mentioned in particular. A memory device according to the DDR II standard can output up to 16 data bits simultaneously at the 16 data outputs, depending on the organization. If, for example, all data have the same switching direction, i.e. a low high transition, this results in decelerated switch edges through on-chip voltage drops on the on-chip supply voltage lines. Thereby, the useable data eye is reduced.
An off-chip driver (OCD) consists typically of a circuitry, which is referred to as output driver, a prestage and other circuit parts. The output driver can be constructed in a very simple way. In a simple embodiment, it basically consists only of pMOS field-effect transistors, which pull the output to a positive potential (pull up function) and of nMOS field-effect transistors, which pull the output to a low potential (pull down function). The pMOS and nMOS field-effect transistors are basically connected like in an inverter, however, the gate terminals are controlled by separate prestages for increasing flexibility.
In a circuit variation of an off-chip driver (OCD), control of the gate terminals of the prestage transistors is performed by using current sources. In contrary to a voltage control, this circuit variation has the advantage that the steepness of the switch edges is well controlled at an intermediate node between the prestage and the output driver, which means at the gate terminals of the output transistors. This increases the precision of the edge steepness at the output of the off-chip driver and thus contributes to an insensitivity of the data eye against interferences. In this circuit variation, charging of the gate capacitance of the output transistors is controlled by a current source. With fixed gate capacitance, a well defined increase of the gate source voltage at the output transistor results. As a result, the transistor is switched on in a well controlled manner and the edge of the data eye has a predetermined slope. Switching on a pMOS field-effect transistor in the output stage of the off-chip driver is performed with the aid of a nMOS field-effect transistor connected as current source. This reduces the gate potential of the pMOS field-effect transistor. Switching on an nMOS field-effect transistor in the output stage of the off-chip driver is performed by a pMOS field-effect transistor connected as current source. This increases the gate potential of the nMOS field-effect transistor whereby the nMOS field-effect transistor is switched on.
FIG. 3 shows a detail of a circuit diagram of an off-chip driver according to the prior art. The off-chip driver is designated with 300 in its entirety. The off-chip driver 300 comprises a p prestage 310, a n prestage 312 as well as an output driver 314. The output driver 314 comprises a pMOS field-effect transistor 320 as well as an nMOS field-effect transistor 322. The pMOS field-effect transistor 320 and the nMOS field-effect transistor 322 are connected in a similar way as an inverter, wherein the gate terminal of the pMOS field-effect transistor 320 is controlled by the p prestage 310 with a p prestage output signal 321, and the gate terminal of the nMOS field-effect transistor 322 is controlled by the n prestage 312 with an n prestage output signal 323. The source terminal of the nMOS field-effect transistor 322 is connected to a reference potential VSSQ. The source terminal of the pMOS field-effect transistor 320 is connected to a supply potential VDDQ, which is positive relative to the reference potential VSSQ. As in an inverter, the drain terminals of the pMOS field-effect transistor 320 and the nMOS field-effect transistor 322 are connected to each other and to an output terminal 320, to which thus an output stage output signal 332 is applied.
The p prestage 310 comprises a CMOS inverter 340 as well as another nMOS field-effect transistor 342. As usual, the CMOS inverter 340 consists of a pMOS field-effect transistor 350 as well as an nMOS field-effect transistor 352 and has a first supply voltage terminal 354 as well as a second supply voltage terminal 356. The gate terminals of the two field-effect transistors 350, 352 are both connected to a data input 360, where a prestage input signal 362 is applied. The output of the CMOS inverter 340 controls the pMOS field-effect transistor 320 of the output driver 314. The source terminal of the pMOS field-effect transistor 350 is connected to the positive supply potential VDDQ. The source terminal of the nMOS field-effect transistor 352 is connected to the drain terminal of the nMOS field-effect transistor 342, which serves as current source transistor. Thus, the drain terminal of the transistor represents a current output 366. The source terminal of the current source transistor 342, which forms a base terminal 368, is connected to the reference potential VSSQ. The gate terminal of the current source transistor 342 is connected to a current source control circuit 370 and receives a current source control signal 372.
The n prestage 312 is structured complementary to the p prestage 310.
Based on the structural description, the mode of operation of the off-chip driver 300 will be described below. The output driver 314 switches the external output 330 to a high or low logic level, in dependence on the control signals of the p prestage 310 and the n prestage 312. The output of the pMOS field-effect transistor 320 pulls the external output 330 to a level close to the supply potential VDDQ, when a low logic level is applied to the gate terminal of the pMOS field-effect transistor 320. The output of the nMOS field-effect transistor 322 pulls the external output 330 to a level close to the reference potential VSSQ, when a high logic level is applied to the gate terminal. It has to be considered that either the gate source potential of the nMOS field-effect transistor 322 and the pMOS field-effect transistor 320 determines the current which the respective field-effect transistor can supply. The gate source voltage of the prestage transistors 320, 322 can thus not change instantaneously. Rather, the gate capacitance has to be charge-reversed for each of the transistors to obtain a change of the current flow through the respective transistor. The rate, at which the gate capacitance of an output stage transistor 320, 322 can be charge-reversed is finally a measure for the steepness of the output signal at the external terminal 330. The charge-reverse time is determined by the amount of the respective gate capacitance as well as the available control current Ip, In. The gate capacitance is mainly determined by the dimensions of the transistor and the thickness of the gate oxide. The dimensions of the transistor are mainly determined by the required output current as well as by technological standards. In the same way, the thickness of the gate oxide can not simply be varied, since it is determined by the technological standards. Thus, it is desirable to be able to determine the gate current Ip, In for the output stage transistors 320, 322. As has been explained above, a determination of the respective gate currents allows, a determination of the edge steepness of the external output signal at the external output 330.
Control of the gate current is performed by the prestages 310 or 312, respectively. In the following, the mode of operation of the p prestage 310 will be discussed, an analog description applies to the n prestage 312. The p prestage comprises a current source transistor 342, whose gate source voltage is determined by a current source control circuit 370. Thus, the drain current ID of the current source transistor 342 is a function of the drain source voltage applied to the current source transistor 342. During normal operation of the circuit, the current source transistor 342 knows mainly two states. In the one state, both the drain source voltage and the drain current ID becomes zero. In a second stage, the drain current ID,0, assumes a fixed predetermined value ID,0, which is mainly determined by the current source control circuit 370. The second state is assumed when the drain source voltage of the current source transistor 342 exceeds a predetermined threshold. Then, the output resistance of the current source transistor is very high. The inverter circuit 340 determines, in which of the two states the current source transistor 342 is. If a sufficiently high positive potential (in relation to the reference potential VSSQ) is applied to the input 360 of the inverter circuit, the nMOS field-effect transistor 352 becomes conductive. As long as the potential at the data input 360 is high enough to switch on the nMOS field-effect transistor 352 and to allow a current flow through the current source transistor 342, the current source transistor provides the drain current ID,0, provided the nMOS field-effect transistor 352 is designed for the transmission of a sufficiently large current. The current flowing in this mode of operation charges the gate source capacitance of the pMOS output stage field-effect transistor 320. If the gate potential of the pMOS output stage field-effect transistor 320 drops, the current through the drain source path of the nMOS inverter field-effect transistor 352 and through the current source transistor 342 decreases also. Thus, a static equilibrium state is established.
Further, it has to be noted that two conditions have to be fulfilled that the current source transistor 342 can provide the current predetermined by the current source control switch 370 to the pMOS output stage field-effect transistor 320. On the one hand, the voltage dropping across the drain source paths of the current source transistor 342 and the nMOS inverter field-effect transistor 352 has to be large enough to operate the respective transistor in saturation. On the other hand, the gate source voltage of the nMOS inverter field-effect transistor 352 has to be sufficiently high above the threshold voltage. If the two conditions are not fulfilled at the same time, the gate electrode of the pMOS output stage field-effect transistor 320 will not be charge-reversed with the intended current ID,0.
Particularly, three situations are possible where despite the presence of a high logic level at the data input 360 of the p prestage 310, the gate capacitance of the pMOS output stage field-effect transistor 320 is not charge-reversed with the intended current. This is inevitably the case when the gate electrode of the pMOS output stage field-effect transistor 320 is already at a very low potential. At such a time, the charge-reverse process is already substantially terminated. Thus, it is neither required nor desirable to charge-reverse the gate capacitance any further. Rather, a static state should be achieved. Thus, this case represents no interference effect.
However, it can happen that the control potential at the data input 360 of the p prestage 310 is not sufficiently high. In that case, the nMOS inverter field-effect transistor 352 does not gate fully, and the current source transistor 342 cannot provide the given current. Such a case can be present when possible interferences in previous stages of a circuitry avoid that the logic level at the data input 360 achieves its full intended value.
On the other hand, an intended current flow can not be achieved, even when the intended potential is applied to the data input 360, but the reference potential VSSQ at the source terminal of the current source transistor rises above the intended value. In that case, the nMOS inverter field-effect transistor 352 and the current source transistor 342 cannot gate fully and the pMOS output stage field-effect transistor 320 does not receive the required control current for obtaining a sufficiently steep-edged output signal at the external terminal 330 at its gate terminal. A rising reference potential VSSQ can be observed, when several adjacent off-chip drivers perform similar switching operations at the same time. Then, a high current flows across the reference potential lines for VSSQ. Unavoidable ohmic voltage drops, which can further be added by the effects of the inductivities caused by bond wires, lead to a significantly noticeable voltage drop. Thus, proper operation of the off-chip driver 300 is no longer ensured.
Further, it should be noted that when a logic level is applied to the data input 360 of the p prestage 310, a corresponding pMOS inverter field-effect transistor 350 becomes conductive. Then, the same discharges the gate capacitance of the pMOS output stage field-effect transistor 320. The corresponding rise time is not critical, since the nMOS output stage field-effect transistor 322, which is mainly responsible for the transition from a high potential to a low potential at the output 330 of the off-chip driver 300, is activated at the same time.
The above-described circuitry has the disadvantage that it can be interfered or shut-down by strong voltage drops on the on-chip supply lines. If the reference potential VSSQ rises extensively, the above-described current source can be shut down, since the corresponding base potential increases. Thereby, the corresponding gate source voltage drops, and the current source is “pinched off”. A similar behavior results for a possibly existing n prestage 312, when the supply potential VDDQ drops excessively.
Thus, the described circuit according to the prior art does not operate reliably when the supply potential and the reference potential, respectively, are subject to strong variations. However, these variations are only hard to avoid when several off-chip drivers switch simultaneously. Thereby, the circuitry according to the prior art has a significant reliability risk. Thus, the usage in high volume products is to be considered as problematical or questionable.